The present invention relates to a technique which automatically designs a semiconductor integrated circuit, and more specifically to a technique which automatically performs processing for equalizing spacing wirings formed in a semiconductor integrated circuit.
With high integration/multifunctioning and the like of a semiconductor integrated circuit, the number of pads in such a semiconductor integrated circuit and the number of external connecting electrodes (i.e., electrode pins) of a semiconductor package have been on the increase in recent years. Therefore, design work for wiring the electrode pins and the pads also has increased in complexity. There has been an increasingly demand for an automated technique for such design work.
As techniques for automating wirings among pads and electrode pins, there have heretofore been known ones disclosed in, for example, the following patent documents 1 through 5 (Japanese Unexamined Patent Publication No. 2000-35986, Japanese Unexamined Patent Publication No. 2000-100955, Japanese Unexamined Patent Publication No. Hei 5(1993)-250441, Japanese Unexamined Patent Publication No. Hei 7(1995)-271836, and Japanese Unexamined Patent Publication No. 2002-83006).
In the patent document 1, the placement area of electrode pins is divided into four trapezoidal areas, and the electrode pins for their divided areas and pads arranged along outline side opposite to the divided areas are wired in accordance with predetermined priorities (refer to paragraphs 0111 through 0120, FIGS. 6 through 9, FIG. 12, etc. in the patent document 1).
In the patent document 2, common pullout patterns for wiring a plurality of pads and a plurality of electrode pins are formed in advance and disposed appropriately, thereby realizing an automatic placement (refer to paragraphs 0039 and 0040 and the like in the patent document 2).
In the patent document 3, on-grid type wire-connection processing and off-grid type wire-connection processing are combined together to attain the shortening of a wire-connection processing time while the occurrence of a unconnected pin pair is being prevented (refer to paragraph 0013 and the like in the patent document 3).
In the patent document 4, a wire spacing arbitrarily determined by a designer is changed to a wire spacing pre-stored in wire spacing memory means to thereby optimize the wire spacing (refer to paragraph 0016 and the like in the patent document 4).
In the patent document 5, a wire spacing arbitrarily determined by a designer is changed to a uniform wire spacing to thereby optimize the wire spacing (refer to paragraphs 0023 and 0024 in the patent document 5).
It is desirable to equalize wire spacings upon design work for the semiconductor integrated circuit. This is because when the wire spacings are not uniform, malfunctions such as deterioration in reliability and moisture resistance due to migration (phenomenon that a metal used as a wiring and an electrode migrates on an insulator), wiring-to-wiring shorts due to a failure in plating, variations in delay time due to variations in parasitic capacitance between wirings, etc. become easy to occur.
In contrast to this, the patent documents 4 and 5 disclose the techniques each of which adjusts the interval between wirings. Thus, the interval between the wirings is made uniform by using these techniques to make it possible to prevent the occurrence of shorts and breaks.
In the technique disclosed in the patent document 4, however, the interval between the wirings is merely changed depending upon the information read from the wire spacing memory means. Therefore, it is satisfactory where wire spacings in a wiring area (refer to, for example, FIG. 10 in the patent document 4) including only vertical and horizontal wirings are adjusted. However, it is difficult to apply the technique to such complex wirings as to contain line segments in an oblique direction.
On the other hand, since the wire spacings are adjusted using arcs or ellipses for correction, the technique of the patent document 5 can be applied to wirings containing line segments extending in an oblique direction. The technique of the patent document 5 is however accompanied by a drawback that computing processing for determining the optimum position of each wiring is complex.